1. Field of the Invention
The invention relates to a correction circuit, and in particular relates to a correction circuit with 50% duty cycle.
2. Description of the Related Art
In general, dynamic random access memory (DRAM) uses a receiver to receive complementary clock signals (VCLK and /VCLK) from an external circuit and generates a main clock signal (MCLK) for internal circuit use. However, due to device mismatch, temperature factor or other factors, the complementary clock signals (VCLK and /VCLK) can be mismatched. In this example, the main clock signal (MCLK) will be shifted and affect a clock signal margin of internal circuits.